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L. Gasparini, O. Zadedyurina, G. Fontana, D. Macii, A. Boni, Y. Ofek, "An Effective Digital Circuit for Jitter Reduction of GPS Synchronization Signals," AMUEM '07- IEEE International Workshop on Advanced Methods for Uncertainty Estimation in Measurement 2007, Sardagna, Trento, Italy, July 16-18 2007.

The GPS satellite constellation is equipped with atomic clocks distributing 1 pulse per second (1-pps) signals to all earth segment users. Such signals can be used for synchronization purposes, provided that the random jitter of the generated 1-pps pulse stream is adequate to the accuracy requirements of the target application. This paper describes a fully digital synchronization circuit whose purpose is to lock and to reduce the jitter of the 1 pulse-per-second signal generated by a low-cost GPS receiver of moderate timing accuracy. The proposed solution provides a good tradeoff between cost, system complexity and achievable accuracy. The synchronization circuit has been implemented into an FPGA.. Its accuracy performance in turn has been estimated experimentally and compared with those of a more expensive commercial synchronization component based on Voltage Controlled Crystal Oscillator (VCXO).

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